STI (shallow trench isolation) structures have been widely used as isolation structures in semiconductor devices. These STI structures facilitate the miniaturization of semiconductor devices since the size of the field region is limited to a desired size of a trench by forming the trench in the semiconductor substrate and filling the trench with insulation material.
Conventionally, in forming a trench isolation structure, a pad oxide film is deposited at a thickness of about 200 Å on a semiconductor substrate. A silicon nitride film is then deposited on the pad oxide film. Subsequently, a photosensitive film is applied and exposed on the silicon nitride film. The photosensitive film is then formed into a pattern by removing only the portion of the photosensitive film covering the region to be processed to define the trench.
Next, the trench is formed in the semiconductor substrate by dry etching the exposed silicon nitride film, the pad oxide film, and the semiconductor substrate up to a predetermined depth while using the photosensitive film pattern as a mask. Subsequently, the photosensitive film pattern is removed. A cleaning process is then performed.
Subsequently, a liner oxide film is formed on an entire surface of the silicon nitride film (including on an inner wall of the trench). A trench oxide film is then thickly deposited on the liner oxide film such that the trench is sufficiently filled.
The trench oxide film is then planarized by a chemical mechanical polishing process until the silicon nitride film is exposed. Finally, the silicon nitride film is removed to complete the trench isolation process.
In the conventional trench isolation structure, stress is concentrated on an edge of the trench. In addition, this edge of the trench is likely hollowed since the liner oxide film and a portion of the trench oxide film are etched together when the silicon nitride film is wet etched. This may make the edge of the trench fragile.
Moreover, as semiconductor devices become more and more integrated, contacts become more susceptible to misalignment with the fragile edge of the trench. This misalignment may cause leakage current due to contact spiking, which may cause fatal defects in the semiconductor device.
Conventional techniques for preventing this leakage current of the trench due to misalignment of the contacts are described in U.S. Pat. Nos. 6,420,770, 6,406,987, 6,403,445, and 6,350,661.
Presently, using up to a 0.18 μm design rule, a contact pattern can be formed with a distance of 0.2–0.3μm between the contact and the trench without misalignment. However, as the semiconductor device becomes more highly integrated, for example, by a 0.15 μm or 0.13 μm design rule and the like in the future, the distance between the contact and the trench becomes 0.1 μm, 0.0 μm, etc, (i.e., there is no margin for the contact alignment), and the current patterning processes cannot integrate the semiconductor device.